1. Technical Field
The invention relates generally to semiconductor interconnects, and more specifically, to chip-to-chip integration and off-chip connection schemes for semiconductor devices.
2. Background Art
A typical electronic system may comprise a variety of electronic components, fabricated on a variety of materials. Very often, it is impossible for these various components to be integrated on a single substrate due to performance considerations or cost concerns. Consequently, these electronic components are packaged and externally electrically interconnected to function as a unit.
In the past, semiconductor packages have been electrically interconnected through wire bonding and/or the use of a C4 flip chip. Unfortunately, as packages become more dense and total performance gain becomes more important for high power chips in the system, the use of wire bonding and flip chips to form off-chip connections is not practical in many applications. Specifically, a significant performance degradation is caused by a wire bond induced parasitic inductance from a chip to a printed circuit board. Although a flip chip overcomes the parasitic inductance problem, the thermal properties of the flip chip severely limit the ability to cool high power chips, and adding an external heat sink to provide thermal conduction causes packaging constraint and increased chip operation ambient temperature.
There are inventions in the past with electronic components stacked together, whereby electrical communication between components are made possible via feed-throughs in the semiconductor bodies. Examples are found in the following U.S. Patents: U.S. Pat. No. 5,128,831, issued to Fox, III et al. in July 1992; U.S. Pat. No. 5,481,133, issued to Hsu in January 1996; U.S. Pat. No. 5,424,245, issued to Gurtler et al. in June 1995; U.S. Pat. No. 5,202,754, issued to Bertin et al. in April 1993; and U.S. Pat. No. 5,270,261, issued to Bertin et al. in December 1993. Although feed-throughs are used in the stacks, the assembled stacks are then attached onto a printed circuit board with the off-chip wiring schemes, long routing traces and all the associated prior art shortfalls. Furthermore, the aforementioned patents do not provide proper heat dissipation for high power chips, and low inductance connections to different levels of packaging, such as a circuit board.